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96 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
DSPLB 3:1 Core-to-PLB Line Write
The timing diagram in Figure 2-27 shows a line write in a system with a PLB clock that
runs at one third the frequency of the PowerPC 405 clock.
The line write (wl1) is requested by the DCU in PLB cycle 2, which corresponds to
PowerPC 405 cycle 4. The BIU responds in the same cycle. The request is made in response
to a flush in PowerPC 405 cycles 1 and 2 (flush1). Data is sent from the DCU to the BIU in
PLB cycles 2 through 5 (PowerPC 405 cycles 4 through 15).
Figure 2-26: DSPLB 2:1 Core-to-PLB Line Read
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CPMC405CLK
UG018_30_101701
PPC405 Outputs:
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUABUS[0:31]
adr1
fill1
C405PLBDCUBE[0:7]
C405PLBDCUWRDBUS[0:63]
C405PLBDCUSIZE2
DCU
rl1
PLB/BIU Outputs:
PLBC405DCUADDRACK
PLBC405DCURDDBUS[0:63]
PLBC405DCURDWDADDR[1:3]
PLBC405DCURDDACK
PLBC405DCUWRDACK
PLBC405DCUBUSY
rl1
rl1
01
rl1
23
rl1
45
rl1
67
d1
01
d1
23
d1
45
d1
67
0246
PLBCLK