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168 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 3: PowerPC 405 OCM Controller
R
Figure 3-16: ISOCM: ISINIT and ISFILL Descriptions (Read Access) for Virtex II-Pro
UG018_69_042304
R
ead Data on DCRDBUS
C
ontent in ISINIT Register
ISINIT (ISOCM Initialization Address)
. . . .
. . . .
D 0
Bit 8
Map to physical address bus to ISBRAM
Bit 0 to Bit 21 ISINIT register value maps to 21 bit initialization address for ISOCMBRAMWRABUS [ 8:28 ].
This address is incremented by 1 for every write into ISFILL register.
Bit 29 is used to interface to the processor block to generate the ISOCMBRAMEVENWRITEEN and
ISOCMBRAMODDWRITEEN outputs.
D 1
Bit 9
D 19
Bit 27
D 20
Bit 28
D 21
Bit 29
I
SOCMBRAMWRABUS[ 8:28 ]
. . . .
A 8 A 9 A 27 A 28 A 29
R
ead Data on DCRDBUS
C
ontent in ISFILL Register
ISFILL (ISOCM Fill Data Register)
. . . .
. . . .
D 0
Bit 0
Map to physical write data bus to ISBRAM
32 bits ISFILL register value for ISOCM, used to send instructions via DCR into ISOCM memory space
D 1
Bit 1
D 28
Bit 28
D 29
Bit 29
D 30
Bit 30
D 31
Bit 31
I
SOCMBRAMWRDBUS[ 0:31 ]
. . . .
D 0 D 1 D 28 D 29 D 30 D 31