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180 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 3: PowerPC 405 OCM Controller
R
Figure 3-28: Single Cycle Mode (1:1) DSOCM Write Variable Latency Virtex-4
UG018_64c_12080
3
C
PMC405Clock
D
SOCM 1:1 Data Store Timing (Variable latency, DSOCMRDWRCOMPLETE driven by OCM slaves)
B
RAMDSOCMCLK
Byte_wr_1 Byte_wr_2
S_addr_1 S_addr_2
St_data_1 St_data_2
valid next valid
D
SOCMWRADDRVALID
(
To BRAM or Slave)
W
rite Complete
(
From BRAM or Slave)
D
SOCMBRAMBYTEWRITE[0:3]
(
To BRAM or Slave)
S
tore Address
(
To BRAM or Slave)
W
rite Data
(
To BRAM or Slave)
complete complete
Figure 3-29: Multi Cycle Mode (1:2) DSOCM Write Variable Latency Virtex-4
UG018_65c_12080
3
C
PMC405Clock
D
SOCM 2:1 Data Store Timing (Variable latency, DSOCMRDWRCOMPLETE driven by OCM slaves)
B
RAMDSOCMCLK
D
SOCMWRADDRVALID
(
To BRAM or Slave)
W
rite Complete
(
From BRAM or Slave)
D
SOCMBRAMBYTEWRITE[0:3]
(
To BRAM or Slave)
S
tore Address
(
To BRAM or Slave)
W
rite Data
(
To BRAM or Slave)
Byte_wr_1 Byte_wr_2
S_addr_1 S_addr_2
St_data_1 St_data_2
valid next valid
complete complete