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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 65
UG018 (v2.0) August 20, 2004 1-800-255-7778
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in cycles 10 through 15). The line is not cacheable, so instructions are not transferred from
the fill buffer to the instruction cache.
ISPLB Pipelined Non-Cacheable Sequential Fetch
The timing diagram in Figure 2-11 shows two consecutive eight-word line fetches that are
address pipelined. The example assumes the instructions are not cacheable. It also assumes
the instructions are fetched sequentially from the end of the first line through the end of the
second line. As with the previous example, it provides an illustration of how all
instructions in a line must be transferred even though some of the instructions are
discarded.
The first line read (rl1) is requested by the ICU in cycle 3 in response to a cache miss
(represented by the miss1 transaction in cycles 1 and 2). Instructions are sent from the BIU
to the ICU fill buffer in cycles 4 through 7. The target instruction is bypassed to the
instruction fetch unit in cycle 5 (byp1). Because the instructions are executing sequentially,
the target instruction is the only instruction in the line that is executed. The line is not
cacheable, so instructions are not transferred from the fill buffer to the instruction cache.
After the first miss is detected, the ICU performs a prefetch in anticipation of requiring
instructions from the next cache line (represented by the prefetch2 transaction in cycles 3
and 4). The second line read (rl2) is requested by the ICU in cycle 5 in response to the
prefetch. After the first line is read from the BIU, instructions for the second line are sent
from the BIU to the ICU fill buffer. This occurs in cycles 8 through 11. These instructions
overwrite the instructions from the previous line. After loading into the fill buffer,
instructions from the second line are bypassed to the instruction fetch unit to prevent a
processor stall during sequential execution (represented by the byp2 transaction in cycles 9
through 14). The line is not cacheable, so instructions are not transferred from the fill buffer
to the instruction cache.
Figure 2-10: ISPLB Non-Pipelined Non-Cacheable Sequential Fetch
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_15_101701
PPC405 Outputs:
C405PLBICUREQUEST
C405PLBICUABUS[0:29]
adr1 adr2
byp1 byp2miss2miss1
ICU
rl2rl1
rl2rl1
PLB/BIU Outputs:
PLBC405ICUADDRACK
PLBC405ICURDDBUS[0:63]
PLBC405ICURDWDADDR[1:3]
PLBC405ICURDDACK
rl1
67
rl1
01
rl1
23
rl1
45
rl2
01
rl2
23
rl2
45
rl2
67
d1
67
d1
01
d1
23
d1
45
d2
01
d2
23
d2
45
d2
67
6024 0246
PLBC405ICUBUSY