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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 87
UG018 (v2.0) August 20, 2004 1-800-255-7778
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The second line read (rl2) is requested by the DCU in cycle 4. The BIU responds to this
request after it has completed all transactions associated with the first request (rl1). Data is
sent from the BIU to the DCU fill buffer in cycles 7 through 10. After all data associated
with this line is read, it is transferred by the DCU from the fill buffer to the data cache. This
is represented by the fill2 transaction in cycles 11 through 13.
The third line read (rl3) cannot be requested until the first request (rl1) is complete. The
earliest this request can occur is in cycle 7. However, the request is delayed to cycle 10
because the DCU is busy transferring the fill buffer to the data cache in cycles 7 through 9
(fill1). The BIU responds to the rl3 request after it has completed all transactions associated
with the second request (rl2). Data is sent from the BIU to the DCU fill buffer in cycles 11
through 14. After all data associated with this line is read, it is transferred by the DCU from
the fill buffer to the data cache. This is represented by the fill3 transaction in cycles 15
through 17.
DSPLB Line Read/Word Read/Line Read
The timing diagram in Figure 2-18 shows a sequence involving an eight-word line read, a
word read, and another an eight-word line read. These requests are address-pipelined
between the DCU and BIU. The line reads are cacheable and the word read is not
cacheable.
The first line read (rl1) is requested by the DCU in cycle 2 and the BIU responds in the same
cycle. Data is sent from the BIU to the DCU fill buffer in cycles 3 through 6. After all data
associated with this line is read, it is transferred by the DCU from the fill buffer to the data
cache. This is represented by the fill1 transaction in cycles 7 through 9.
The word read (rw2) is requested by the DCU in cycle 4. The BIU responds to this request
after it has completed all transactions associated with the first request (rl1). A single word
Figure 2-17: DSPLB Three Consecutive Line Reads
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_21_101701
PPC405 Outputs:
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUABUS[0:31]
adr1 adr2 adr3
fill1 fill2 fill3
C405PLBDCUBE[0:7]
C405PLBDCUWRDBUS[0:63]
C405PLBDCUSIZE2
DCU
rl2 rl3rl1
PLB/BIU Outputs:
PLBC405DCUADDRACK
PLBC405DCURDDBUS[0:63]
PLBC405DCURDWDADDR[1:3]
PLBC405DCURDDACK
PLBC405DCUWRDACK
PLBC405DCUBUSY
rl2 rl3rl1
rl1
01
rl1
23
rl1
45
rl1
67
rl2
01
rl2
23
rl2
45
rl2
67
rl3
01
rl3
23
rl3
45
rl3
67
d1
01
d1
23
d1
45
d1
67
d2
01
d2
23
d2
45
d2
67
d3
01
d3
23
d3
45
d3
67
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