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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 35
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Clock and Power Management Interface
The clock and power management (CPM) interface enables power-sensitive applications
to control the processor clock using external logic. The OCM controllers are clocked
separately from the processor core. In addition to this, the Virtex-4-FX family PowerPC 405
also use separate clocks for the APU and DCR controller. Two types of processor clock
control are possible:
x Global local enables control a clock zone within the processor. These signals are used to
disable the clock splitters within a zone so that the clock signal is prevented from
propagating to the latches within the zone. The PowerPC 405 is divided into three
clock zones: core, timer, and JTAG. Control over a zone is exercised as follows:
i The core clock zone contains most of the logic comprising the PowerPC 405 core
and controllers. It does not contain logic that belongs to the timer or JTAG zones,
or other logic within the processor block. The core zone is controlled by the
CPMC405CPUCLKEN signal.
i The timer clock zone contains the PowerPC 405 timer logic. It does not contain
logic that belongs to the core or JTAG zones, or other logic within the processor
block. This zone is separated from the core zone so that timer events can be used
to “wake up” the core logic if a power management application has put it to sleep.
The timer zone is controlled by the CPMC405TIMERCLKEN signal.
i The JTAG clock zone contains the PowerPC 405 JTAG logic. It does not contain
logic that belongs to the core or timer zones, or other logic within the processor
block. The JTAG zone is controlled by the CPMC405JTAGCLKEN signal.
Although an enable is provided for this zone, the JTAG standard does not allow
local gating of the JTAG clock. This enables basic JTAG functions to be maintained
when the rest of the chip (including the CPM FPGA macro) is not running.
x Global gating controls the toggling of the PowerPC 405 clock, CPMC405CLOCK.
Instead of using the global-local enables to prevent the clock signal from propagating
through a zone, CPM logic can stop the PowerPC 405 clock input from toggling. If this
method of power management is employed, the clock signal should be held active
(logic 1). The CPMC405CLOCK is used by the core and timer zones, but not the JTAG
zone.
CPM logic should be designed to wake the PowerPC 405 from sleep mode when any of the
following occurs:
i A timer interrupt or timer reset is asserted by the PowerPC 405.
i A chip-reset or system-reset request is asserted (this request comes from a source
other than the PowerPC 405).
i An external interrupt or critical interrupt input is asserted and the corresponding
interrupt is enabled by the appropriate machine-state register (MSR) bit.
BRAM BlockSelect RAM Outside
XXX Unspecified FPGA unit Outside
a. Not to be confused with the OCM controllers, which are located inside the processor block.
Table 2-1: Signal Name Prefix Definitions (Continued)
Prefix1 or Prefix2 Definition Location