Filter
Top Products
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 227
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
Table C-3: Parameters Relative to the DCR Bus Clock (CPMDCRCLK, Virtex-4 Only)
Parameter Function Signals
Setup/Hold:
T
PPCDCK
_EXDCRACK
T
PPCCKD
_EXDCRACK
Control Inputs EXTDCRC405ACK
T
PPCDCK
_EXDCRDBUS
T
PPCCKD
_EXCDRDBUS
Data Inputs EXTDCRC405DBUSIN[0:31]
Clock to Out:
T
PPCCKO
_EXDCRRD Control Outputs EXTDCRREAD
T
PPCCKO
_EXDCRWR EXTDCRWRITE
T
PPCCKO
_EXDCRABUS Address Outputs EXTDCRABUS[0:9]
T
PPCCKO
_EXDCRDBUSO Data Outputs EXTDCRDBUSOUT[0:31]
Clock:
T
DCRPWH
Clock Pulse Width, High
State
CPMDCRCLK
T
DCRPWL
Clock Pulse Width, Low State CPMCDCRCLK