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94 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
DSPLB Word Write/Line Read/Line Write
The timing diagram in Figure 2-25 shows a sequence involving a word write, an eight-
word line read, and an eight-word line write. It demonstrates how read and write
operations can overlap due to the split read-data and write-data busses.
The word write (ww1) is requested by the DCU in cycle 2 and the BIU responds in the same
cycle. A single word is sent from the DCU to the BIU in cycle 2. The BIU uses the byte
enables to select the appropriate bytes from the write-data bus.
The line read (rl2) is address pipelined with the previous word write. The rl2 request is
made by the DCU in cycle 4 and the BIU responds in the same cycle. Data is sent from the
BIU to the DCU fill buffer in cycles 5 through 8. After all data associated with this line is
read, it is transferred by the DCU from the fill buffer to the data cache. This is represented
by the fill2 transaction in cycles 9 through 11.
The line write (wl3) is address pipelined with the previous line read. The wl3 request is
made by the DCU in cycle 6 in response to the cache flush in cycles 4 through 5 (flush3).
The BIU responds to the wl3 request in the same cycle it is asserted by the DCU. Data is
sent from the DCU to the BIU in cycles 6 through 9. Because of the split data bus, the write
operations in cycles 6 through 8 overlap read operations from the previous read request
(rl2).
Figure 2-24: DSPLB Word Write/Word Read/Word Write/Line Read
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_28_101701
PPC405 Outputs:
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUABUS[0:31]
adr1 adr2 adr3 adr4
val val val
d1 d3
C405PLBDCUBE[0:7]
C405PLBDCUWRDBUS[0:63]
C405PLBDCUSIZE2
DCU
rw2 rl4ww1 ww3
PLB/BIU Outputs:
PLBC405DCUADDRACK
PLBC405DCURDDBUS[0:63]
PLBC405DCURDWDADDR[1:3]
PLBC405DCURDDACK
PLBC405DCUWRDACK
PLBC405DCUBUSY
ww3ww1
rw2 rl4ww1 ww3
rw2 rl4
01
rl4
23
rl4
45
rl4
67
d2
d4
01
d4
23
d4
45
d4
67
0246
fill4