Xilinx UG018 Yard Vacuum User Manual


 
80 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
PLBC405DCUADDRACK (Input)
When asserted, this signal indicates the PLB slave acknowledges the DCU data-access
request (indicated by the DCU assertion of C405PLBDCUREQUEST). When deasserted, no
such acknowledgement exists. A data-access request can be acknowledged by the PLB
slave in the same cycle the request is asserted by the DCU. The PLB slave must latch the
following data-access request information in the same cycle it asserts the request
acknowledgement:
x C405PLBDCURNW, which specifies whether the data-access request is a read or a
write.
x C405PLBDCUABUS[0:31], which contains the address of the data-access request.
x C405PLBDCUSIZE2, which indicates the transfer size of the data-access request.
x C405PLBDCUCACHEABLE, which indicates whether the data address is cacheable.
x C405PLBDCUWRITETHRU, which specifies the caching policy of the data address.
x C405PLBDCUU0ATTR, which indicates the value of the user-defined storage
attribute for the instruction-fetch address.
x C405PLBDCUGUARDED, which indicates whether the data address is in guarded
storage.
During the acknowledgement cycle, the PLB slave must return its bus width indicator (32
bits or 64 bits) using the PLBC405DCUSSIZE1 signal.
The acknowledgement signal remains asserted for one cycle. In the next cycle, both the
data-access request and acknowledgement are deasserted. The PLB slave can begin
receiving data from the DCU in the same cycle the address is acknowledged. Data can be
sent to the DCU beginning in the cycle after the address acknowledgement. The PLB slave
Table 2-15: Contents of DCU Write-Data Bus During Eight-Word Line Transfer
PLB-Slave
Size
Transfer
DCU Write-Data Bus
[0:31]
DCU Write-Data Bus
[32:63]
32-Bit First Word 0 Not Applicable
Second Word 1
Third Word 2
Fourth Word 3
Fifth Word 4
Sixth Word 5
Seventh Word 6
Eighth Word 7
64-Bit First Word 0 Word 1
Second Word 2 Word 3
Third Word 4 Word 5
Fourth Word 6 Word 7