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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 235
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
processor reset
See core reset.
programmable-interval timer
See PIT.
R
read acknowledge
data-side PLB
82
instruction-side PLB 56
read not write 74
read request 68
address pipelining 71
cacheable 70
DCR 105
unaligned operands 71
without allocate 70
read-data bus
data-side PLB
82
DCR 106
instruction-side PLB 56
real mode, definition of 23
registers
supported by PPC405
23
request
chip reset
45
core reset 45
critical interrupt 111
data-side PLB 73
instruction-side PLB 52
noncritical interrupt 111
system reset 45
reset
chip
43, 45, 46
core or processor 43, 45, 46
global set reset 137
interface requirements 43
system 43, 45, 46
watchdog time-out 39
S
signal name prefixes 34
signal summary 213
signals
CPM interface
36
CPU control interface 41
data-side PLB interface 71
DCR interface 103
debug interface 128
EIC interface 110
instruction-side PLB interface 50
JTAG interface 111
naming conventions 34
reset interface 44
summary 213
trace interface 131
slave size
data-side PLB
81
instruction-side PLB 55
sleep mode 37
request 39
waking 35
special-purpose register
See SPR.
split data bus
68
overlapped operations 92, 94
SPR 25
storage attributes 28
system reset 43, 46
request 45
T
timer clock zone 35, 37
timer exception 39
timing models
PPC405
223
TLB 27
trace interface 131
disable 134
even execution status 133
odd execution status 133
signals 131
trace cycle 133
trace status 134
trigger event 132
trigger event in 134
trigger event type 132
transfer order
data-side PLB
83
instruction-side PLB 57
transfer size
data-side PLB
74
instruction-side PLB 53
translation look-aside buffer
See TLB.
trigger events
131
U
U0 attribute
data-side PLB
76
instruction-side PLB 54
UISA
See PowerPC.
unaligned operands
71
unconditional debug event 130
user mode, definition of 22
V
VEA 19
See PowerPC.
virtual mode, definition of
23
W
watchdog timer
See WDT.
WDT
description of
29
reset request 39
timer exception 39
update frequency 38
write acknowledge 83
write request 68
address pipelining 71
DCR 105
non-cacheable 70
unaligned operands 71
without allocate 70
write-data bus
data-side PLB
79
DCR 106
write-through cacheability 75