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124 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
signal TDO_PPC : std_logic;
signal TMS_PPC : std_logic;
signal TDI_PPC : std_logic;
signal TCK_PPC : std_logic;
begin
-- Component Instantiation
U_PPC1 : PPC405
port map (
...
JTGC405TCK => TCK_PPC,
JTGC405TDI => TDI_PPC,
JTGC405TMS => TMS_PPC,
JTGC405TRSTNEG => 1,
C405JTGTDO => TDO_PPC,
JTGC405BNDSCANTDO => open,
C405JTGTDOEN => TDO_TS_PPC,
C405JTGEXTEST => open,
C405JTGCAPTUREDR => open,
C405JTGSHIFTDR => open,
C405JTGUPDATEDR=> open,
05JTGPGMOUT=> open,
...
);
U_JTAG : JTAGPPC
port map (
TDOTSPPC => TDO_TS_PPC,
TDOPPC => TDO_PPC,
TMS => TMS_PPC,
TDIPPC => TDI_PPC,
TCK => TCK_PPC
);
end SINGLE_PPC_JTAG_SERIAL_arch;
// Module: SINGLE_PPC_JTAG_SERIAL
// Description: Verilog instantiation template for serial connection of
// a single PPC405 core to dedicated JTAG logic
module SINGLE_PPC_JTAG_SERIAL ();
wire TDO_TS_PPC;
wire TDO_PPC;
wire TMS_PPC;
wire TDI_PPC;
wire TCK_PPC;
// Component Instantiation
PPC405 U_PPC1(
...
.JTGC405TCK (TCK_PPC),
.JTGC405TDI (TDI_PPC),
.JTGC405TMS (TMS_PPC),
.JTGC405TRSTNEG (1’b1),