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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 15
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
OEA The PowerPC operating-environment architecture, which
defines the memory-management model, supervisor-level
registers and instructions, synchronization requirements, the
exception model, and the time-base resources as seen by
supervisor programs.
on chip In system-on-chip implementations, this indicates on the same
FPGA chip as the processor core, but external to the processor
core.
pending As applied to interrupts, this indicates that an exception
occurred, but the interrupt is disabled. The interrupt occurs
when it is later enabled.
physical address The address used to access physically-implemented memory.
This address can be translated from the effective address. When
address translation is not used, this address is equal to the
effective address.
PLB Processor local bus.
privileged mode The operating mode typically used by system software.
Privileged operations are allowed and software can access all
registers and memory.
problem state Synonym for user mode.
process A program (or portion of a program) and any data required for
the program to run.
real address Synonym for physical address.
scalar Individual data objects and instructions. Scalars are of arbitrary
size.
set To write a bit value of 1.
sleep A state in which the PowerPC 405 processor clock is prevented
from toggling. The execution state of the PowerPC 405 does not
change when in the sleep state.
sticky A bit that can be set by software, but cleared only by the
processor. Alternatively, a bit that can be cleared by software,
but set only by the processor.
string A sequence of consecutive bytes.
supervisor state Synonym for privileged mode.
system memory Physical memory installed in a computer system external to the
processor core, such RAM, ROM, and flash.
tag As applied to caches, a set of address bits used to uniquely
identify a specific cache line within a congruence class. As
applied to TLBs, a set of address bits used to uniquely identify
a specific entry within the TLB.