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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 31
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
caches and the time associated with performing cache-line fills and flushes. Unless stated
otherwise, the number of cycles described applies to systems having zero-wait-state
memory access.
Table 1-3: PowerPC 405 Cycles per Instruction
Instruction Class Execution Cycles
Arithmetic 1
Trap 2
Logical 1
Shift and Rotate 1
Multiply (32-bit, 48-bit, 64-bit results, respectively) 1, 2, 4
Multiply Accumulate 1
Divide 35
Load 1
Load Multiple and Load String (cache hit) 1 per data transfer
Store 1
Store Multiple and Store String (cache hit or miss) 1 per data transfer
Move to/from device-control register 3
Move to/from special-purpose register 1
Branch known taken 1 or 2
Branch known not taken 1
Predicted taken branch 1 or 2
Predicted not-taken branch 1
Mispredicted branch 2 or 3