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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 199
UG018 (v2.0) August 20, 2004 1-800-255-7778
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FCM Interface Timing Specification
Autonomous Transactions
Note: Actual timing results may vary from those shown in Figure 4-3. For example, the instruction
and operands can be valid on the same FCM clock cycle, or they can be many cycles apart.
Figure 4-3: APU Controller Decoded Autonomous Transaction Example
UG018_04_02_042304
CPMFCMCLK
APUFCMINSTRUCTION
APUFCMINSTRVALID
APUFCMDECODED
APUFCMRADATA/
APUFCMRBDATA
APUFCMOPERANDVALID
FCMAPUDONE
APUFCMWRITEBACKOK
FCMAPUSLEEPNOTREADY
APUFCMDECUDI[0:2]
APUFCMDECUDIVALID