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166 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 3: PowerPC 405 OCM Controller
R
DCR Write Access
As shown in Figure 3-15, ISINIT is a 22-bit register (A8-A29) that is mapped to DCR write
data bus bits D8-D29. The write address on the memory interface is A8-A28, and address
bit A29 is used to control the ISOCMBRAMODDWRITEEN and
ISOCMBRAMEVENWRITEEN signals. Additionally, in Virtex-4, the
ISOCMDCRBRAMEVENEN and ISOCMDCRBRAMODDEN signals can be used to select
the corresponding BRAMs in which to write. Each time register ISFILL is written, there is
one 32-bit instruction written into the BRAM (odd or even, depending on the value of
address bit A29).
Figure 3-15: ISOCM: ISINIT and ISFILL Descriptions (Write Access) for Virtex-II Pro and Virtex-4
UG018_68_05120
4
W
rite Data on DCRDBUS
C
ontent in ISINIT Register
ISINIT (ISOCM Initialization Address)
. . . .
. . . .
D 8
Bit 8
Map to physical address bus to ISBRAM
Bits 8 to 28 of the ISINIT register value maps to the 21 bit initialization address for ISOCMBRAMWRABUS [8:28].
The address represented by A8 to A29 is increased by 1 for every write into the ISFILL register.
In Virtex-II Pro, Bit 29 is used to interface to the processor block to generate the ISOCMBRAMEVENWRITEEN and
ISOCMBRAMODDWRITEEN outputs. In Virtex-4, this bit also controls ISOCMDCRBRAMEVENEN and
ISOCMDCRBRAMMODDEN signals. This allows separate control of the BRAMEN signal for odd and even BRAMs.
D 9
Bit 9
D 27
Bit 27
D 28
Bit 28
D 29
Bit 29
I
SOCMBRAMWRABUS[ 8:28 ]
. . . .
A 8 A 9 A 27 A 28 A 29
W
rite Data on DCRDBUS
C
ontent in ISFILL Register
ISFILL (ISOCM Fill Data Register)
. . . .
. . . .
D 0
Bit 0
Map to physical write data bus to ISBRAM
32 bits ISFILL register value for ISOCM, used to send instructions via DCR into ISOCM memory space.
D 1
Bit 1
D 28
Bit 28
D 29
Bit 29
D 30
Bit 30
D 31
Bit 31
I
SOCMBRAMWRDBUS[ 0:31 ]
. . . .
D 0 D 1 D 28 D 29 D 30 D 31