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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 127
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
U_JTAG : JTAGPPC
port map (
TDOTSPPC => TDO_TS_PPC,
TDOPPC => TDO_OUT2,
TMS => TMS_PPC,
TDIPPC => TDI_PPC,
TCK => TCK_PPC
);
end TWO_PPC_JTAG_SERIAL_arch;
// Module: TWO_PPC_JTAG_SERIAL
// Description: Verilog instantiation template for serial connection of
// two PPC405 cores to dedicated JTAG logic
module TWO_PPC_JTAG_SERIAL ();
wire TDO_TS_PPC;
wire TMS_PPC;
wire TDI_PPC;
wire TCK_PPC;
wire TDO_OUT1;
wire TDO_OUT2;
wire TDO_TS_OUT1;
wire TDO_TS_OUT2;
or o1(TDO_TS_PPC, TDO_TS_OUT1, TDO_TS_OUT2);
// Component Instantiation
PPC405 U_PPC1(
...
.JTGC405TCK (TCK_PPC),
.JTGC405TDI (TDI_PPC),
.JTGC405TMS (TMS_PPC),
.JTGC405TRSTNEG (1’b1),
.C405JTGTDO (TDO_OUT1),
.JTGC405BNDSCANTDO (),
.C405JTGTDOEN (TDO_TS_OUT1),
.C405JTGEXTEST (),
.C405JTGCAPTUREDR (),
.C405JTGSHIFTDR (),
.C405JTGUPDATEDR (),
.C405JTGPGMOUT (),
...
);
PPC405 U_PPC2(
...
.JTGC405TCK (TCK_PPC),
.JTGC405TDI (TDO_OUT1),
.JTGC405TMS (TMS_PPC),
.JTGC405TRSTNEG (1’b1),
.C405JTGTDO (TDO_OUT2),