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20 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 1: Introduction to the PowerPC 405 Processor
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Table 1-2: OEA Features of the PowerPC Embedded-Environment Architecture
Operating
Environment
Features
Register model x Privileged special-purpose registers (SPRs) and instructions for accessing those
registers
x Device control registers (DCRs) and instructions for accessing those registers
Storage model
x Privileged cache-management instructions
x Storage-attribute controls
x Address translation and memory protection
x Privileged TLB-management instructions
Exception model
x Dual-level interrupt structure supporting various exception types
x Specification of interrupt priorities and masking
x Privileged SPRs for controlling and handling exceptions
x Interrupt-control instructions
x Specification of how partially executed instructions are handled when an interrupt
occurs
Debug model
x Privileged SPRs for controlling debug modes and debug events
x Specification for seven types of debug events
x Specification for allowing a debug event to cause a reset
x The ability of the debug mechanism to freeze the timer resources
Time-keeping model
x 64-bit time base
x 32-bit decrementer (the programmable-interval timer)
x Three timer-event interrupts:
i Programmable-interval timer (PIT)
i Fixed-interval timer (FIT)
i Watchdog timer (WDT)
x Privileged SPRs for controlling the timer resources
x The ability to freeze the timer resources using the debug mechanism
Synchronization
requirements
x Requirements for special registers and the TLB
x Requirements for instruction fetch and for data access
x Specifications for context synchronization and execution synchronization
Reset and initialization
requirements
x Specification for two internal mechanisms that can cause a reset:
i Debug-control register (DBCR)
i Timer-control register (TCR)
x Contents of processor resources after a reset
x The software-initialization requirements, including an initialization code example