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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 139
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Chapter 3
PowerPC 405 OCM Controller
Introduction
The On-Chip Memory (OCM) controller serves as a dedicated interface between the FPGA
BRAMs and the OCM signals contained within the embedded PPC405 core. The OCM
controller provides non-cacheable access to instruction-side and data-side memory spaces.
The data-side interface supports a 32-bit, bi-directional memory interface, and the
instruction-side interface supports a 64-bit unidirectional memory interface. Unlike the
Processor Local Bus (PLB) interface, the OCM controller does not require bus arbitration to
access the FPGA fabric resources. Each OCM controller is capable of addressing up to
16 MB of memory, however, the amount of BRAM in the device may limit the maximum
size of OCM supported. Typical applications of data-side OCM (DSOCM) for the Virtex-II
Pro and Virtex-4 product families can utilize the dual-port feature of BRAMs to enable both
read and write data transfer between processor and FPGA. One possible application for
instruction-side OCM (ISOCM) is the storage of interrupt service routines. In addition, its
non-cacheable feature eliminates cache pollution and thrashing.
In the Virtex-II Pro family, the DSOCM and ISOCM controllers are designed to interface
specifically to BRAMs with fixed latencies.
In the Virtex-4 family, the DSOCM controller has an enhanced feature to support memory-
mapped peripherals via additional control signals. This extended feature enables the
DSOCM controller to interface to multiple BRAM blocks with different latencies, as well as
to slave peripherals with variable latencies. In addition, the ISOCM controller in Virtex-4
has an improved interface for software debugging.
The enhanced features that exist only within the Virtex-4 family will be clearly labeled
“Virtex-4 Only.” Otherwise, the description applies to both Virtex-II Pro and Virtex-4.
The following topics are covered in this chapter:
x “Comparison of Virtex-II Pro and Virtex-4 OCM Controllers”
x “Functional Features”
x “OCM Controller Operation”
x “Programmer's Model”
x “Timing Specification for Fixed Latency (Virtex-4 and Virtex-II Pro)”
x “Timing Specification for Variable Latency (Virtex-4 DSOCM Controller Only)”
x “Application Notes and Reference Designs”
x “References”