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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 13
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Terms
TCR Timer-control register
TSR Timer-status register
Table 1-2: PowerPC 405 Registers (Continued)
Register Descriptive Name
active As applied to signals, this term indicates a signal is in a state
that causes an action to occur in the receiving device, or
indicates an action occurred in the sending device. An active-
high signal drives a logic 1 when active. An active-low signal
drives a logic 0 when active.
assert As applied to signals, this term indicates a signal is driven to its
active state.
atomic access A memory access that attempts to read from and write to the
same address uninterrupted by other accesses to that address.
The term refers to the fact that such transactions are indivisible.
big endian A memory byte ordering where the address of an item
corresponds to the most-significant byte.
Book-E An version of the PowerPC architecture designed specifically
for embedded applications.
cache block Synonym for cache line.
cache line A portion of a cache array that contains a copy of contiguous
system-memory addresses. Cache lines are 32-bytes long and
aligned on a 32-byte address.
cache set Synonym for congruence class.
clear To write a bit value of 0.
clock Unless otherwise specified, this term refers to the PowerPC 405
processor clock.
congruence class A collection of cache lines with the same index.
cycle The time between two successive rising edges of the associated
clock.
dead cycle A cycle in which no useful activity occurs on the associated
interface.
deassert As applied to signals, this term indicates a signal is driven to its
inactive state.
dirty An indication that cache information is more recent than the
copy in memory.
doubleword Eight bytes, or 64 bits.
effective address The untranslated memory address as seen by a program.