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68 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
Data-Side Processor Local Bus Interface
The data-side processor local bus (DSPLB) interface enables the PowerPC 405 data cache
unit (DCU) to load (read) and store (write) data from any memory device connected to the
processor local bus (PLB). This interface has a dedicated 32-bit address bus output, a
dedicated 64-bit read-data bus input, and a dedicated 64-bit write-data bus output. The
interface is designed to attach as a master to a 64-bit PLB, but it also supports attachment
as a master to a 32-bit PLB. The interface is capable of one data transfer (64 or 32 bits) every
PLB cycle.
At the chip level, the DSPLB can be combined with the instruction-side read-data bus (also
a PLB master) to create a shared read-data bus. This is done if a single PLB arbiter services
both PLB masters and the PLB arbiter implementation only returns data to one PLB master
at a time.
Refer to the PowerPC Processor Reference Guide for more information on the operation of the
PowerPC 405 DCU.
Data-Side PLB Operation
Data-access (read and write) requests are produced by the DCU and communicated over
the PLB interface. A request occurs when an access misses the data cache or the memory
location that is accessed is non-cacheable. A data-access request contains the following
information:
x The request is indicated by C405PLBDCUREQUEST. See “C405PLBDCUREQUEST
(Output)”.
x The type of request (read or write) is indicated by C405PLBDCURNW. See
“C405PLBDCURNW (Output)”.
Figure 2-14: ISPLB Aborted Fetch Request
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_17_101701
PPC405 Outputs:
miss2miss1
ICU
C405PLBICUREQUEST
C405PLBICUABUS[0:29]
adr1 adr2
rl2rl1
C405PLBICUABORT
rl2rl1
PLB/BIU Outputs:
PLBC405ICUADDRACK
PLBC405ICURDDBUS[0:63]
PLBC405ICURDWDADDR[1:3]
PLBC405ICURDDACK
rl2
01
rl2
23
rl2
45
rl2
67
d2
01
d2
23
d2
45
d2
67
0246
PLBC405ICUBUSY