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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 145
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
DSOCM Ports
Figure 3-2 and Figure 3-3 are the block diagrams of the DSOCM in Virtex-4 and Virtex-II
Pro. All signals are in big endian format.
Figure 3-2: DSOCM Interface for Virtex-4
UG018_37b_12080
3
RESET
DSOCMBRAMABUS[8:29]
BRAMDSOCMRDDBUS[0:31]
DSOCMBRAMWRDBUS[0:31]
DSOCMBRAMBYTEWRITE[0:
3]
BRAMDSOCMCLK
DSOCMRDWRCOMPLETE
(Virtex-4 Only)
CPMC405CLOCK
DSCNTLVALUE[0:7]
DSARCVALUE[0:7]
DSOCMBRAMEN
DSOCMBUSY
DSOCMRDADDRVALID
(Virtex-4 Only)
DSOCMWRADDRVALID
(Virtex-4 Only)
Clock & Reset are
s
ame signals that go
into CPU; therefore,
no separate Clock &
Reset are required.
Data-Side
On-Chip Memory
(DSOCM) Controller
Figure 3-3: DSOCM Interface for Virtex-II Pro
DSOCMBRAMEN
DSOCMBUSY
UG018_37_020102
RESET
DSOCMBRAMABUS[8:29]
BRAMDSOCMRDDBUS[0:31]
DSOCMBRAMWRDBUS[0:31]
DSOCMBRAMBYTEWRITE[0:3]
BRAMDSOCMCLK
CPMC405CLOCK
DSCNTLVALUE[0:7]
DSARCVALUE[0:7]
TIEDSOCMDCRADDR[0:7]
Clock & Reset are
same signals that go
into CPU; therefore,
no separate Clock &
Reset are required.
Data-Side
On-Chip Memory
(DSOCM) Controller