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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 21
UG018 (v2.0) August 20, 2004 1-800-255-7778
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PowerPC 405 Software Features
The PowerPC 405 processor core is an implementation of the PowerPC embedded-
environment architecture. The processor provides fixed-point embedded applications with
high performance at low power consumption. It is compatible with the PowerPC UISA.
Much of the PowerPC 405 VEA and OEA support is also available in implementations of
the PowerPC Book-E architecture. Key software features of the PowerPC 405 include:
x A fixed-point execution unit fully compliant with the PowerPC UISA:
i 32-bit architecture, containing thirty-two 32-bit general purpose registers (GPRs).
x PowerPC embedded-environment architecture extensions providing additional
support for embedded-systems applications:
i True little-endian operation
i Flexible memory management
i Multiply-accumulate instructions for computationally intensive applications
i Enhanced debug capabilities
i 64-bit time base
i 3 timers: programmable interval timer (PIT), fixed interval timer (FIT), and
watchdog timer (all are synchronous with the time base)
x Performance-enhancing features, including:
i Static branch prediction
i Five-stage pipeline with single-cycle execution of most instructions, including
loads and stores
i Multiply-accumulate instructions
i Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle
divide)
i Enhanced string and multiple-word handling
i Support for unaligned loads and unaligned stores to cache arrays, main memory,
and on-chip memory (OCM)
i Minimized interrupt latency
x Integrated instruction-cache:
i 16 KB, 2-way set associative
i Eight words (32 bytes) per cache line
i Fetch line buffer
i Instruction-fetch hits are supplied from the fetch line buffer
i Programmable prefetch of next-sequential line into the fetch line buffer
i Programmable prefetch of non-cacheable instructions: full line (eight words) or
half line (four words)
i Non-blocking during fetch line fills
x Integrated data-cache:
i 16 KB, 2-way set associative
i Eight words (32 bytes) per cache line
i Read and write line buffers
i Load and store hits are supplied from/to the line buffers