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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 67
UG018 (v2.0) August 20, 2004 1-800-255-7778
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ISPLB 3:1 Core-to-PLB Line Fetch
The timing diagram in Figure 2-13 shows an eight-word line fetch in a system with a PLB
clock that runs at one third the frequency of the PowerPC 405 clock.
The line read (rl1) is requested by the ICU in PLB cycle 2, which corresponds to PowerPC
405 cycle 4. The BIU responds in the same cycle. Instructions are sent from the BIU to the
ICU fill buffer in PLB cycles 3 through 6 (PowerPC 405 cycles 7 through 18). After all
instructions associated with this line are read, the line is transferred by the ICU from the fill
buffer to the instruction cache (not shown).
ISPLB Aborted Fetch Request
The timing diagram in Figure 2-14 shows an aborted fetch request. The request is aborted
because of an instruction-flow change, such as a taken branch or an interrupt. It shows the
earliest-possible subsequent fetch-request that can be produced by the ICU.
The first line read (rl1) is requested by the ICU in cycle 3 in response to a cache miss
(represented by the miss1 transaction in cycles 1 and 2). The BIU responds in the same
cycle the request is made by the ICU. However, the processor also aborts the request in
cycle 3, possibly because a branch was mispredicted or an interrupt occurred. Therefore,
the BIU ignores the request and does not transfer instructions associated with the request.
The change in control flow causes the ICU to fetch instructions from a non-sequential
address. The second line read (rl2) is requested by the ICU in cycle 7 in response to a cache
miss of the new instructions. (represented by the miss2 transaction in cycles 5 and 6).
Instructions are sent from the BIU to the ICU fill buffer in cycles 8 through 11.
Figure 2-13: ISPLB 3:1 Core-to-PLB Line Fetch
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CPMC405CLK
UG018_19_101701
PPC405 Outputs:
C405PLBICUREQUEST
C405PLBICUABUS[0:29]
adr1
rl1
rl1
PLB/BIU Outputs:
PLBC405ICUADDRACK
PLBC405ICURDDBUS[0:63]
PLBC405ICURDWDADDR[1:3]
PLBC405ICURDDACK
rl1
01
rl1
23
rl1
45
rl1
67
d1
01
d1
23
d1
45
d1
67
0246
miss1
ICU
PLBCLK
PLBC405ICUBUSY