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48 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
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x The request priority is indicated by C405PLBICUPRIORITY[0:1]. See
“C405PLBICUPRIORITY[0:1] (Output)”. The PLB arbiter uses this information to
prioritize simultaneous requests from multiple PLB masters.
The processor can abort a PLB fetch request using C405PLBICUABORT. See
“C405PLBICUABORT (Output)”. This can occur when a branch instruction is executed or
when an interrupt occurs.
Fetched instructions are returned to the ICU by a PLB slave device over the PLB interface.
A fetch response contains the following information:
x The fetch-request address is acknowledged by the PLB slave using
PLBC405ICUADDRACK. See “PLBC405ICUADDRACK (Input)”.
x Instructions sent from the PLB slave to the ICU during a line transfer are indicated as
valid using PLBC405ICURDDACK. See “PLBC405ICURDDACK (Input)”.
x The PLB-slave bus width, or size (32-bit or 64-bit), is specified by PLBC405ICUSSIZE1.
See “PLBC405ICUSSIZE1 (Input)”. The PLB slave is responsible for packing data
bytes from non-word devices so that the information sent to the ICU is presented
appropriately, as determined by the transfer size.
x The instructions returned to the ICU by the PLB slave are sent using four-word or
eight-word line transfers, as specified by the transfer size in the fetch request. These
instructions are returned over the ICU read-data bus, PLBC405ICURDDBUS[0:63].
See “PLBC405ICURDDBUS[0:63] (Input)”. Line transfers operate as follows:
i A four-word line transfer returns the quadword aligned on the address specified
by C405PLBICUABUS[0:27]. This quadword contains the target instruction
requested by the ICU. The quadword is returned using two doubleword or four
word transfer operations, depending on the PLB slave bus width (64-bit or 32-bit,
respectively).
i An eight-word line transfer returns the eight-word cache line aligned on the
address specified by C405PLBICUABUS[0:26]. This cache line contains the target
instruction requested by the ICU. The cache line is returned using four
doubleword or eight word transfer operations, depending on the PLB slave bus
width (64-bit or 32-bit, respectively).
x The words returned during a line transfer can be sent from the PLB slave to the ICU in
any order (target-word-first, sequential, other). This transfer order is specified by
PLBC405ICURDWDADDR[1:3]. See “PLBC405ICURDWDADDR[1:3] (Input)”.
Interaction with the ICU Fill Buffer
As mentioned above, the PLB slave can transfer instructions to the ICU in any order
(target-word-first, sequential, other). When instructions are received by the ICU from the
PLB slave, they are placed in the ICU fill buffer. When the ICU receives the target
instruction, it forwards it immediately from the fill buffer to the instruction-fetch unit so
that pipeline stalls due to instruction-fetch delays are minimized. This operation is referred
to as a bypass. The remaining instructions are received from the PLB slave and placed in the
fill buffer. Subsequent instruction fetches read from the fill buffer if the instruction is
already present in the buffer. For the best possible software performance, the PLB slave
should be designed to return the target word first.
Non-cacheable instructions are transferred using a four-word or eight-word line-transfer
size. Software controls this transfer size using the non-cacheable request-size bit in the core-
configuration register (CCR0[NCRS]). This enables non-cacheable transfers to take
advantage of the PLB line-transfer protocol to minimize PLB-arbitration delays and bus
delays associated with multiple, single-word transfers. The transferred instructions are