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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 49
UG018 (v2.0) August 20, 2004 1-800-255-7778
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placed in the ICU fill buffer, but not in the instruction cache. Subsequent instruction fetches
from the same non-cacheable line are read from the fill buffer instead of requiring a
separate arbitration and transfer sequence across the PLB. Instructions in the fill buffer are
fetched with the same performance as a cache hit. The non-cacheable line remains in the fill
buffer until the fill buffer is needed by another line transfer.
Cacheable instructions are always transferred using an eight-word line-transfer size. The
transferred instructions are placed in the ICU fill buffer as they are received from the PLB
slave. Subsequent instruction fetches from the same cacheable line are read from the fill
buffer during the time the line is transferred from the PLB slave. When the fill buffer is full,
its contents are transferred to the instruction cache. Software can prevent this transfer by
setting the fetch without allocate bit in the core-configuration register (CCR0[FWOA]). In
this case, the cacheable line remains in the fill buffer until the fill buffer is needed by
another line transfer. An exception is that the contents of the fill buffer are always
transferred if the line was fetched because an icbt instruction was executed.
Prefetch and Address Pipelining
A prefetch is a request for the eight-word cache line that sequentially follows the current
eight-word fetch request. Prefetched instructions are fetched before it is known that they
are needed by the sequential execution of software.
The ICU can overlap a single prefetch request with the prior fetch request. This process,
known as address pipelining, enables a second address to be presented to a PLB slave while
the slave is returning data associated with the first address. Address pipelining can occur
if a prefetch request is produced before all instructions from the previous fetch request are
transferred by the slave. This capability maximizes PLB-transfer throughput by reducing
dead cycles between instruction transfers associated with the two requests. The ICU can
pipeline the prefetch with any combination of sequential, branch, and interrupt fetch
requests. A prefetch request is communicated over the PLB two or more cycles after the
prior fetch request is acknowledged by the PLB slave.
Address pipelining of prefetch requests never occurs under any one of the following
conditions:
x The PLB slave does not support address pipelining.
x The prefetch address falls outside the 1 KB physical page holding the current fetch
address. This limitation avoids potential problems due to protection violations or
storage-attribute mismatches.
x Non-cacheable transfers are programmed to use a four-word line-transfer size
(CCR0[NCRS]
0).
x For non-cacheable transfers, prefetching is disabled (CCR0[PFNC] 0).
x For cacheable transfers, prefetching is disabled (CCR0[PFC] 0).
Address pipelining of non-cacheable prefetch requests can occur if all of the following
conditions are met:
x Address pipelining is supported by the PLB slave.
x The ICU is not already involved in an address-pipelined PLB transfer.
x A branch or interrupt does not modify the sequential execution of the current (first)
instruction-fetch request.
x Non-cacheable prefetching is enabled (CCR0[PFNC] 1).
x A non-cacheable instruction-prefetch is requested, and the instruction is not in the fill
buffer or being returned over the ISOCM interface.