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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 83
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
PLBC405DCURDWDADDR[1:3] (Input)
These signals are used to specify the transfer order. They identify which word or
doubleword of an eight-word line transfer is present on the DCU read-data bus when the
PLB slave returns instructions to the DCU. The words returned during a line transfer can
be sent from the PLB slave to the DCU in any order (target-word-first, sequential, other).
The transfer-order signals are valid when the read-data acknowledgement signal
(PLBC405DCURDDACK) is asserted. This acknowledgment is asserted for one cycle per
transfer. There is no limit to the number of cycles between two transfers. The transfer-order
signals are not valid when the read-data acknowledgement signal is deasserted.
These signals are ignored by the processor during single word transfers.
Table 2-16 shows the location of data on the DCU read-data bus as a function of PLB-slave
size and transfer order when an eight-word line read occurs. In this table, the “Transfer
Order” column contains the possible values of PLBC405DCURDWDADDR[1:3]. For 64-bit
PLB slaves, PLBC405DCURDWDADDR[3] should always be 0 during a transfer. In this
case, the transfer order is invalid if this signal asserted. For 32-bit slaves, the connection to
a 64-bit master shown in Figure 2-16, page 77 is assumed.
PLBC405DCUWRDACK (Input)
When asserted, this signal indicates the PLB slave latched the data on the write-data bus
sent from the DCU (write data is acknowledged). The DCU holds this data valid until the
end of the cycle this signal is asserted. In the following cycle, the DCU presents new data
and holds it valid until acknowledged by the PLB slave. This continues until all write data
Table 2-16: Contents of DCU Read-Data Bus During Eight-Word Line Transfer
PLB-Slave
Size
Transfer
Order
a
a. An “x” indicates a don’t-care value in PLBC405DCURDWDADDR[1:3].
DCU Read-Data Bus
[0:31]
DCU Read-Data Bus
[32:63]
32-Bit 000 Word 0 Word 0
001 Word 1 Word 1
010 Word 2 Word 2
011 Word 3 Word 3
100 Word 4 Word 4
101 Word 5 Word 5
110 Word 6 Word 6
111 Word 7 Word 7
64-Bit 000 Word 0 Word 1
010 Word 2 Word 3
100 Word 4 Word 5
110 Word 6 Word 7
xx1 Invalid