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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 109
UG018 (v2.0) August 20, 2004 1-800-255-7778
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DCR Interface 1:2 Clocking, Latched Acknowledge
The example in Figure 2-36 assumes the following:
x The PowerPC 405 DCR interface is clocked at half the frequency of the peripheral
containing the addressed DCR.
x The acknowledge signal is latched and forwarded with the DCR bus as shown in
Figure 2-31, page 103.
x After the acknowledge signal is asserted, it is not deasserted until the appropriate
read-access or write-access request signal is deasserted.
External DCR Timing Consideration (Virtex-II Pro/ProX Only)
Users need to be aware that there is no DCR clock input to the processor block of the
Virtex-II Pro and Virtex-II ProX devices. When dealing with signals that cross CPU clock
domain and DCR clock domain, users may want to add re-synchronization flip-flops to
simply timing constraints, or set up appropriate multi-cycle/false path constraints in the
UCF file.
An example for the re-synchronization of DCR interface can be found in Xilinx Embedded
Development Kit (EDK). Please refer to the Virtex-II Pro PowerPC405 wrapper IP in the
“Processor IP Reference Guide” for details.
The Virtex-4-FX family does have a DCR clock input and does not have the
synchronization issues mentioned here.
External Interrupt Controller Interface
The PowerPC embedded-environment architecture defines two classes of interrupts:
critical and noncritical. The interrupt handler for an external critical interrupt is located at
exception-vector offset 0x0100. The interrupt handler for an external noncritical interrupt
is located at exception-vector offset 0x0200. Generally, the processor prioritizes critical
Figure 2-36: DCR Interface 1:2 Clocking, Latched Acknowledge
Cy cle
CPMC405CLOCK (Virtex-II Pro)/
CPMDCRCLK (Virtex-4 FX)
DCR (FPGA) Clock
UG018_44_032504
DCRWRITE/DCRREAD
DCRABUS[0:9]
PPC405 Outputs:
DCRDBUSOUT[0:31]
DCRDBUSIN[0:31]
DCRACK
DCR Outputs:
data0 data1
addr0
addr1
data0
data1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Note: Abbreviated signal names are used.