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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 47
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Table 2-5, page 44 shows the valid combinations of the RSTC405RESETCORE,
RSTC405RESETCHIP, and RSTC405RESETSYS signals and their effect on the DBSR[MRR]
field following reset.
JTGC405TRSTNEG (Input)
This input is the JTAG test reset (TRST) signal. It can be connected to the chip-level TRST
signal. Although optional in IEEE Standard 1149.1, this signal is automatically used by the
processor block during power-on reset to properly reset all processor block logic, including
the JTAG and debug logic. When deasserted, no JTAG test reset exists.
This is a negative active signal.
Instruction-Side Processor Local Bus Interface
The instruction-side processor local bus (ISPLB) interface enables the PowerPC 405
instruction cache unit (ICU) to fetch (read) instructions from any memory device
connected to the processor local bus (PLB). The ICU cannot write to memory. This interface
has a dedicated 30-bit address bus output and a dedicated 64-bit read-data bus input. The
interface is designed to attach as a master to a 64-bit PLB, but it also supports attachment
as a master to a 32-bit PLB. The interface is capable of one transfer (64 or 32 bits) every PLB
cycle.
At the chip level, the ISPLB can be combined with the data-side read-data bus (also a PLB
master) to create a shared read-data bus. This is done if a single PLB arbiter services both
PLB masters, and the PLB arbiter implementation only returns data to one PLB master at a
time.
Refer to the PowerPC Processor Reference Guide for more information on the operation of the
PowerPC 405 ICU.
Instruction-Side PLB Operation
Fetch requests are produced by the ICU and communicated over the PLB interface. Fetch
requests occur when an access misses the instruction cache or when the accessed memory
location is non-cacheable. A fetch request contains the following information:
x A fetch request is indicated by C405PLBICUREQUEST. See “C405PLBICUREQUEST
(Output)”.
x The target address of the instruction to be fetched is specified by the address bus,
C405PLBICUABUS[0:29]. See “C405PLBICUABUS[0:29] (Output)”. Bits 30:31 of the
32-bit instruction-fetch address are always zero and must be tied to zero at the PLB
arbiter. The ICU always requests an aligned doubleword of data, so the byte enables
are not used.
x The transfer size is specified as four words (quadword) or eight words (cache line)
using C405PLBICUSIZE[2:3]. See “C405PLBICUSIZE[2:3] (Output)”. The remaining
bits of the transfer size (0:1) must be tied to zero at the PLB arbiter.
x The cacheability storage attribute is indicated by C405PLBICUCACHEABLE. See
“C405PLBICUCACHEABLE (Output)”. Cacheable transfers are always performed
with an eight-word transfer size.
x The user-defined storage attribute is indicated by C405PLBICUU0ATTR. See
“C405PLBICUU0ATTR (Output)”.