Xilinx UG018 Yard Vacuum User Manual


 
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 25
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Special-Purpose Registers
The processor contains a number of 32-bit special-purpose registers (SPRs). SPRs provide
access to additional processor resources, such as the count register, the link register, debug
resources, timers, interrupt registers, and others. Most SPRs are accessed only by
privileged software, but a few, such as the count register and link register, are accessed by
all software.
Machine-State Register
The 32-bit machine-state register (MSR) contains fields that control the operating state of the
processor. This register can be accessed only by privileged software.
Condition Register
The 32-bit condition register (CR) contains eight 4-bit fields, CR0–CR7. The values in the CR
fields can be used to control conditional branching. Arithmetic instructions can set CR0
and compare instructions can set any CR field. Additional instructions are provided to
perform logical operations and tests on CR fields and bits within the fields. The CR can be
accessed by all software.
Device Control Registers
The 32-bit device control registers (not shown) are used to configure, control, and report
status for various external devices that are not part of the PowerPC 405 processor. The
OCM controllers are examples of devices that contain DCRs. Although the DCRs are not
part of the PowerPC 405 implementation, they are accessed using the mtdcr and mfdcr
instructions. The DCRs can be accessed only by privileged software.
PowerPC 405 Hardware Organization
As shown in Figure 1-2, the PowerPC 405 processor contains the following elements:
x A 5-stage pipeline consisting of fetch, decode, execute, write-back, and load write-
back stages
x A virtual-memory-management unit that supports multiple page sizes and a variety
of storage-protection attributes and access-control options
x Separate instruction-cache and data-cache units
x Debug support, including a JTAG interface
x Three programmable timers
The following sections provide an overview of each element. Refer to the PowerPC
Processor Reference Guide for more information on how software interacts with these
elements.