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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 69
UG018 (v2.0) August 20, 2004 1-800-255-7778
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x The target address of the data to be accessed is specified by the address bus,
C405PLBDCUABUS[0:31]. See “C405PLBDCUABUS[0:31] (Output)”.
x The transfer size is specified as a single word or as eight words (cache line) using
C405PLBDCUSIZE2. See “C405PLBDCUSIZE2 (Output)”. The remaining bits of the
transfer size (0, 1, and 3) must be tied to zero at the PLB arbiter.
x The byte enables for single-word accesses are specified using C405PLBDCUBE[0:7]
(see “C405PLBDCUBE[0:7] (Output)”). The byte enables specify one, two, three, or
four contiguous bytes in either the upper or lower four byte word of the 64-bit data
bus. The byte enables are not used by the processor during line transfers and must be
ignored by the PLB slave.
x The cacheability storage attribute is indicated by C405PLBDCUCACHEABLE. See
“C405PLBDCUCACHEABLE (Output)”. Cacheable transfers are performed using
word or line transfer sizes.
x The write-through storage attribute is indicated by C405PLBDCUWRITETHRU. See
“C405PLBDCUWRITETHRU (Output)”.
x The guarded storage attribute is indicated by C405PLBDCUGUARDED. See
“C405PLBDCUGUARDED (Output)”.
x The user-defined storage attribute is indicated by C405PLBDCUU0ATTR. See
“C405PLBDCUU0ATTR (Output)”.
x The request priority is indicated by C405PLBDCUPRIORITY[0:1]. See
“C405PLBDCUPRIORITY[0:1] (Output)”. The PLB arbiter uses this information to
prioritize simultaneous requests from multiple PLB masters.
The processor can abort a PLB data-access request using C405PLBDCUABORT. See
“C405PLBDCUABORT (Output)”. This occurs only when the processor is reset.
Data is returned to the DCU by a PLB slave device over the PLB interface. The response to
a data-access request contains the following information:
x The address of the data-access request is acknowledged by the PLB slave using
PLBC405DCUADDRACK. See “PLBC405DCUADDRACK (Input)”.
x Data sent during a read transfer from the PLB slave to the DCU over the read-data bus
are indicated as valid using PLBC405DCURDDACK. See “PLBC405DCURDDACK
(Input)”. Data sent during a write transfer from the DCU to the PLB slave over the
write-data bus are indicated as valid using PLBC405DCUWRDACK. See
“PLBC405DCUWRDACK (Input)”.
x The PLB-slave bus width, or size (32-bit or 64-bit), is specified by
PLBC405DCUSSIZE1. See “PLBC405DCUSSIZE1 (Input)”. The PLB slave is
responsible for packing (during reads) or unpacking (during writes) data bytes from
non-word devices so that the information sent to the DCU is presented appropriately,
as determined by the transfer size.
x The data transferred between the DCU and the PLB slave is sent as a single word or as
an eight-word line transfer, as specified by the transfer size in the data-access request.
Data reads are transferred from the PLB slave to the DCU over the DCU read-data
bus, PLBC405DCURDDBUS[0:63]. See “PLBC405DCURDDBUS[0:63] (Input)”. Data
writes are transferred from the DCU to the PLB slave over the DCU write-data bus,
C405PLBDCUWRDBUS[0:63]. See “C405PLBDCUWRDBUS[0:63] (Output)”. Data
transfers operate as follows:
i A word transfer moves the entire word specified by the address of the data-access
request. The specific bytes being accessed are indicated by the byte enables,
C405PLBDCUBE[0:7]. See “C405PLBDCUBE[0:7] (Output)”. The word is
transferred using one transfer operation.