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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 219
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
FCMAPUDONE V-4 I FCM 0 Indicates the completion of the
instruction in the FCM to the APU
Controller
FCMAPUEXCEPTION V-4 I FCM 0 FCM generate program exception on
the processor (vector 0x0700).
FCMAPUEXEBLOCKINGMCO V-4 I FCM 0 FCM decoded multi cycle operation of
blocking class.
FCMAPUEXECRFIELD[0:2] V-4 I FCM 0 FCM decoded instruction selects
which of the eight PowerPC CR
FCMAPUEXENONBLOCKINGMCO V-4 I FCM 0 FCM decoded multi cycle operation of
non-blocking class.
FCMAPUFPUOP V-4 I FCM 0 FCM decoded FPU instruction.
FCMAPUINSTRACK V-4 I FCM 0 Valid instruction decoded in FCM
FCMAPULOADWAIT V-4 I FCM 0 FCM is not yet ready to receive next
load data.
FCMAPURESULT[0:31] V-4 I FCM 0 FCM execution result passed to the
CPU
FCMAPURESULTVALID V-4 I FCM 0 Values on the FCMAPURESULT[0:31],
FCMAPUXEROV, FCMAPUXERCA
and FCMAPUCR[0:3] are valid.
FCMAPUSLEEPNOTREADY V-4 I FCM 0 Indicates to the APU Controller that
the FCM is still executing
FCMAPUXERCA V-4 I FCM 0 FCM carry status bit.
FCMAPUXEROV V-4 I FCM 0 FCM overflow status bit.
ISARCVALUE[0:7] V-II Pro
and V-4
I ISOCM 0 Power-on base address for the
instruction-side on-chip memory
ISCNTLVALUE[0:7] V-II Pro
and V-4
IISOCMBit 3=1
All
others=0
Power-on configuration of the ISOCM
controller
ISOCMBRAMEN V-II Pro
and V-4
OISOCMNo
Connect
BRAM read enable from the ISOCM
controller
ISOCMDCRBRAMEVENEN V-4 O ISOCM No
Connect
Even word write enable to BRAM via a
DCR-based access
ISOCMDCRBRAMODDEN V-4 O ISOCM No
Connect
Odd word write enable to BRAM via a
DCR-based access
ISOCMBRAMRDABUS[8:28] V-II Pro
and V-4
OISOCMNo
Connect
Read address from ISOCM to BRAM
ISOCMBRAMWRABUS[8:28] V-II Pro
and V-4
OISOCMNo
Connect
Write address from the ISOCM to
BRAM via a DCR-based access
ISOCMBRAMWRDBUS[0:31] V-II Pro
and V-4
OISOCMNo
Connect
Write data from the ISOCM to BRAM
via a DCR-based access
ISOCMDCRBRAMEVENEN V-4 O ISOCM No
Connect
BRAM enable (even bank) for a DCR-
based access
ISOCMDCRBRAMODDEN V-4 O ISOCM No
Connect
BRAM enable (odd bank) for a DCR-
based access
Table B-1: PowerPC 405 Interface Signals in Alphabetical Order (Continued)
Signal
FPGA
Type
a
I/O
Type
Interface
If Unused
Ties To:
b
Function