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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 151
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Note: For backward compatibility with Virtex-II Pro, when connecting DSOCM to BRAM (as shown
in Figure 3-5), set DSOCMRWCOMPLETE to logic 1 and leave the DSOCMRDADDRVALID and
DSOCMWRADDRVALID signals unconnected.
Figure 3-5: DSOCM to BRAM Interface: 8-KByte Example for Virtex-4
UG018_48b_042304
DSOCMBRAMABUS[19:29]
DSOCMBRAMWRDBUS[0:31]
DSOCMBRAMBYTEWRITE[0:3]
BRAMDSOCMCLK
DSOCMBRAMEN
BRAMDSOCMRDDBUS[0:31]
DSCNTLVALUE[0:7]
DSARCVALUE[0:7]
DSOCMRWCOMPLETE
(Virtex-4 Only)
DSOCMRDADDRVALID, n/c
(Virtex-4 Only)
DSOCMWRADDRVALID, n/c
(Virtex-4 Only)
'1'
ADDRA[10:0]
DIA[7:0]
DOA[7:0]
WEA
CLKA
SSRA
ENA*
(RAMB16S9S9) X 4
ADDRB[13:3]
PORT A
PORT B
DIB[7:0]
DOB[7:0]
WEB
To/from FPGA logic
(application-specific use
)
CLKB
ENB
SSRB
(BRAMDSOCMCLK from DCM)
*ENA can be tied off
permanently for higher
performance.
Global signals from FPGA
system interface
Note: n/c = no connect