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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 229
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
T
PCKDO
_FCM Data Outputs APUFCMINSTRUCTION[0:31]
APUFCMRADATA[0:31]
APUFCMRBDATA[0:31]
APUFCMLOADDATA[0:31]
Clock:
T
fcmpwh
and T
FCMPWL
Clock High Width
Clock Low Width
CPMFCMCLK
Table C-4: Parameters Relative to the FCM Clock (CPMFCMCLK, Virtex-4 Only) (Continued)
Parameter Function Signals
Table C-5: Parameters Relative to the PLB Clock (PLBCLK)
Parameter Function Signals
Setup/Hold:
T
PCCK
_PLB/T
PCKC
_PLB Control inputs PLBC405DCUADDRACK
PLBC405DCUBUSY
PLBC405DCUERR
PLBC405DCURDDACK
PLBC405DCUSSIZE1
PLBC405DCUWRDACK
PLBC405ICURDWDADDR[1:3]
PLBC405DCURDWDADDR[1:3]
PLBC405ICUADDRACK
PLBC405ICUBUSY
PLBC405ICUERR
PLBC405ICURDDACK
PLBC405ICUSSIZE1
T
PDCK
_PLB/T
PCKD
_PLB Data inputs PLBC405ICURDDBUS[0:63]
PLBC405DCURDDBUS[0:63]
Clock to Out:
T
PCKCO
_PLB Control outputs C405PLBDCUABORT
C405PLBDCUBE[0:7]
C405PLBDCUCACHEABLE
C405PLBDCUGUARDED
C405PLBDCUPRIORITY[0:1]
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUSIZE2
C405PLBDCUU0ATTR
C405PLBDCUWRITETHRU
C405PLBICUABORT
C405PLBICUCACHEABLE
C405PLBICUPRIORITY[0:1]
C405PLBICUREQUEST
C405PLBICUSIZE[2:3]
C405PLBICUU0ATTR