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108 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
DCR Interface 2:1 Clocking, Latched Acknowledge
The example in Figure 2-35 assumes the following:
x The PowerPC 405 DCR interface is clocked at twice the frequency of the peripheral
containing the addressed DCR.
x The acknowledge signal is latched and forwarded with the DCR bus as shown in
Figure 2-31, page 103.
x After the acknowledge signal is asserted, it is not deasserted until the appropriate
read-access or write-access request signal is deasserted.
Figure 2-34: DCR Interface 1:1 Clocking, Combinatorial Acknowledge
Cy cle
CPMC405CLOCK (Virtex-II Pro)/
CPMDCRCLK (Virtex-4 FX)
DCR (FPGA) Clock
UG018_42_032504
DCRWRITE/DCRREAD
DCRABUS[0:9]
PPC405 Outputs:
DCRDBUSOUT[0:31]
DCRDBUSIN[0:31]
DCRACK
DCR Outputs:
data0 data1 data2
addr0 addr1 addr2
data0 data1 data2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Note: Abbreviated signal names are used.
Figure 2-35: DCR Interface 2:1 Clocking, Latched Acknowledge
Cy cle
CPMC405CLOCK (Virtex-II Pro)/
CPMDCRCLK (Virtex-4 FX)
DCR (FPGA) Clock
UG018_43_042304
DCRWRITE/DCRREAD
DCRABUS[0:9]
PPC405 Outputs:
DCRDBUSOUT[0:31]
DCRDBUSIN[0:31]
DCRACK
DCR Outputs:
data0 data1
addr0 addr1
data0 data1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Note: Abbreviated signal names are used.