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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 183
UG018 (v2.0) August 20, 2004 1-800-255-7778
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Chapter 4
PowerPC 405 APU Controller
This chapter only applies to the PowerPC 405 in the Virtex-4-FX family and covers the
following topics:
x “FCM Instruction Processing”
x “APU Controller Configuration”
x “Interface Definition”
x “FCM Interface Timing Specification”
Note: The Auxiliary Processor Unit (APU) Controller is not available in the Virtex-II Pro family.
Introduction
The Auxiliary Processor Unit (APU) Controller allows the designer to extend the native
PowerPC 405 instruction set with custom instructions that are executed by an FPGA Fabric
Co-processor Module (FCM). This enables a much tighter integration between an
application-specific function and the processor pipeline than is possible using, for
example, a bus peripheral. Figure 4-1 shows the pipeline flow between the PowerPC 405
Core, the APU Controller, and the Fabric Co-processor Module.