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22 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 1: Introduction to the PowerPC 405 Processor
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i Write-back and write-through support
i Programmable load and store cache line allocation
i Operand forwarding during cache line fills
i Non-blocking during cache line fills and flushes
x Support for on-chip memory (OCM) that can provide memory-access performance
identical to a cache hit
x Flexible memory management:
i Translation of the 4 GB logical-address space into the physical-address space
i Independent control over instruction translation and protection, and data
translation and protection
i Page-level access control using the translation mechanism
i Software control over the page-replacement strategy
i Write-through, cacheability, user-defined 0, guarded, and endian (WIU0GE)
storage-attribute control for each virtual-memory region
i WIU0GE storage-attribute control for thirty-two 128 MB regions in real mode
i Additional protection control using zones
x Enhanced debug support with logical operators:
i Four instruction-address compares
i Two data-address compares
i Two data-value compares
i JTAG instruction for writing into the instruction cache
i Forward and backward instruction tracing
x Advanced power management support
The following sections describe the software resources available in the PowerPC 405. Refer
to the PowerPC Processor Reference Guide for more information on using these resources.
Privilege Modes
Software running on the PowerPC 405 can do so in one of two privilege modes: privileged
and user.
Privileged Mode
Privileged mode allows programs to access all registers and execute all instructions
supported by the processor. Normally, the operating system and low-level device drivers
operate in this mode.
User Mode
User mode restricts access to some registers and instructions. Normally, application
programs operate in this mode.
Address Translation Modes
The PowerPC 405 also supports two modes of address translation: real and virtual.