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52 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
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C405PLBICUREQUEST (Output)
When asserted, this signal indicates the ICU is requesting instructions from a PLB slave
device. The PLB slave asserts PLBC405ICUADDRACK to acknowledge the request. The
request can be acknowledged in the same cycle it is presented by the ICU. The request is
deasserted in the cycle after it is acknowledged by the PLB slave. When deasserted, no
unacknowledged instruction-fetch request exists.
The following output signals contain information for the PLB slave device and are valid
when the request is asserted. The PLB slave must latch these signals by the end of the same
cycle during which it acknowledges the request:
x C405PLBICUABUS[0:31] contains the word address of the instruction-fetch request.
x C405PLBICUSIZE[2:3] indicates the instruction-fetch line-transfer size.
x C405PLBICUCACHEABLE indicates whether the instruction-fetch address is
cacheable.
x C405PLBICUU0ATTR indicates the value of the user-defined storage attribute for the
instruction-fetch address.
C405PLBICUPRIORITY[0:1] is also valid when the request is asserted. This signal indicates
the priority of the instruction-fetch request. It is used by the PLB arbiter to prioritize
simultaneous requests from multiple PLB masters.
The ICU supports two outstanding fetch requests over the PLB. The ICU can make a
second fetch request (a prefetch) after the current request is acknowledged. The ICU
deasserts C405PLBICUREQUEST for at least one cycle after the current request is
acknowledged and before the subsequent request is asserted.
If the PLB slave supports address pipelining, it must respond to the two fetch requests in
the order in which they the ICU presents them. All instructions associated with the first
request must be returned before any instruction associated with the second request is
returned. The ICU cannot present a third fetch request until the first request is completed
by the PLB slave. This third request can be presented two cycles after the last read
acknowledge (PLBC405ICURDDACK) is sent from the PLB slave to the ICU, completing
the first request.
The ICU can abort a fetch request if it no longer requires the requested instruction. The ICU
removes a request by asserting C405PLBICUABORT while the request is asserted. In the
next cycle the request is deasserted and remains deasserted for at least one cycle.
C405PLBICUABUS[0:29] (Output)
This bus specifies the memory address of the instruction-fetch request. Bits 30:31 of the 32-
bit address are assumed to be zero so that all fetch requests are aligned on a word
boundary. The fetch address is valid during the time the fetch request signal
(C405PLBICUREQUEST) is asserted. It remains valid until the cycle following
acknowledgement of the request by the PLB slave (the PLB slave asserts
PLBC405ICUADDRACK to acknowledge the request).
C405PLBICUSIZE[2:3] indicates the instruction-fetch line-transfer size. The PLB slave uses
memory-address bits [0:27] to specify an aligned four-word address for a four-word
transfer size. Memory-address bits [0:26] are used to specify an aligned eight-word address
for an eight-word transfer size.