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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 137
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
MCBTIMEREN (Input)
When asserted, this signal indicates that the enable for the timer clock zone
(CPMC405TIMERCLKEN) should follow (match the value of) the global write enable
(GWE) during the FPGA startup sequence. When deasserted, the enable for the timer clock
zone ignores (is independent of) the value of GWE.
MCPPCRST (Input)
When asserted, this signal indicates that the processor block should be reset (the core reset
signal, RSTC405RESETCORE, is asserted) when the global set reset (GSR) signal is
deasserted during the FPGA startup sequence. When MPPCRST is deasserted, the core
reset signal ignores (is independent of) the value of GSR.