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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 121
UG018 (v2.0) August 20, 2004 1-800-255-7778
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For devices with more than one PPC405 core, users must connect the JTAG logic for ALL of
the PPC405 cores on the device when using this connection style, even if some are not
otherwise used. The JTAG signals are the only signals on unused PPC405 cores need to be
connected. The PPC405 core that first sees TDI from the JTAGPPC primitive recognizes the
first four most significant bits in the Instruction Register; the next PPC405 core sees the
next four most significant bits, and so on.
VHDL and Verilog Instantiation Templates
VHDL and Verilog instantiation templates for some connection styles are provided:
x Single PPC Core: Individual Connection to user I/O
(SINGLE_PPC_JTAG_INDIVIDUAL)
x Single PPC Core: Serial Connection through dedicated JTAG pins
(SINGLE_PPC_JTAG_SERIAL)
x Two PPC Cores: Serial Connection through dedicated JTAG pins
(TWO_PPC_JTAG_SERIAL)
For clarity, these instantiation templates only describe connections for the JTAG-related
I/Os on the PPC405 core. Not all PPC405 I/Os are shown.
-- Module: SINGLE_PPC_JTAG_INDIVIDUAL
-- Description: VHDL instantiation template for individual connection
-- of a single PPC405 core to user I/O
library IEEE;
use IEEE.std_logic_1164.all;
entity SINGLE_PPC_JTAG_INDIVIDUAL is
port (
TCK_IN: in std_logic;
TDI_IN: in std_logic;
TMS_IN: in std_logic;
TRSTNEG_IN: in std_logic;
TDO_OUT: out std_logic;
end SINGLE_PPC_JTAG_INDIVIDUAL;
architecture SINGLE_PPC_JTAG_INDIVIDUAL_arch of
SINGLE_PPC_JTAG_INDIVIDUAL is
-- Component Declaration
component PPC405
port(
...
JTGC405TCK: in std_logic;
JTGC405TMS: in std_logic;
JTGC405TDI: in std_logic;
JTGC405TRSTNEG: in std_logic;
C405JTGTDO: out std_logic;
JTGC405BNDSCANTDO: in std_logic;
C405JTGTDOEN: out std_logic;
C405JTGEXTEST: out std_logic;
C405JTGCAPTUREDR: out std_logic;
C405JTGSHIFTDR: out std_logic;
C405JTGUPDATEDR: out std_logic;
C405JTGPGMOUT: out std_logic;
...