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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 27
UG018 (v2.0) August 20, 2004 1-800-255-7778
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read ports and two write ports. During the decode stage, data is read out of the GPRs for
use by the execute unit. During the write-back stage, results are written to the GPR. The
use of five read/write ports on the GPRs allows the processor to execute load/store
operations in parallel with ALU and MAC operations.
The execute unit supports all 32-bit PowerPC UISA integer instructions in hardware, and is
compliant with the PowerPC embedded-environment architecture specification. Floating-
point operations are not supported.
The MAC unit supports implementation-specific multiply-accumulate instructions and
multiply-halfword instructions. MAC instructions operate on either signed or unsigned
16-bit operands, and they store their results in a 32-bit GPR. These instructions can
produce results using either modulo arithmetic or saturating arithmetic. All MAC
instructions have a single cycle throughput.
Exception Handling Logic
Exceptions are divided into two classes: critical and noncritical. The PowerPC 405 CPU
services exceptions caused by error conditions, the internal timers, debug events, and the
external interrupt controller (EIC) interface. Across the two classes, a total of 19 possible
exceptions are supported, including the two provided by the EIC interface.
Each exception class has its own pair of save/restore registers. SRR0 and SRR1 are used for
noncritical interrupts, and SRR2 and SRR3 are used for critical interrupts. The exception-
return address and the machine state are written to these registers when an exception
occurs, and they are automatically restored when an interrupt handler exits using the
return-from-interrupt (rfi) or return-from critical-interrupt (rfci) instruction. Use of
separate save/restore registers allows the PowerPC 405 to handle critical interrupts
independently of noncritical interrupts.
Memory Management Unit
The PowerPC 405 supports 4 GB of flat (non-segmented) address space. The memory-
management unit (MMU) provides address translation, protection functions, and storage-
attribute control for this address space. The MMU supports demand-paged virtual
memory using multiple page sizes of 1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB and
16 MB. Multiple page sizes can improve memory efficiency and minimize the number of
TLB misses. When supported by system software, the MMU provides the following
functions:
x Translation of the 4 GB logical-address space into a physical-address space.
x Independent enabling of instruction translation and protection from that of data
translation and protection.
x Page-level access control using the translation mechanism.
x Software control over the page-replacement strategy.
x Additional protection control using zones.
x Storage attributes for cache policy and speculative memory-access control.
The translation look-aside buffer (TLB) is used to control memory translation and
protection. Each one of its 64 entries specifies a page translation. It is fully associative, and
can simultaneously hold translations for any combination of page sizes. To prevent TLB
contention between data and instruction accesses, a 4-entry instruction and an 8-entry data
shadow-TLB are maintained by the processor transparently to software.