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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 71
UG018 (v2.0) August 20, 2004 1-800-255-7778
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An eight-word line-write transfer occurs when the fill buffer replaces an existing data-
cache line containing modified data. The existing cache line is written to memory before it
is replaced with the fill-buffer contents. The write is performed using a separate PLB
transaction than the previous transfer that caused the replacement. Execution of the dcbf
and dcbst instructions also cause an eight-word line write.
Address Pipelining
The DCU can overlap a data-access request with a previous request. This process, known
as address pipelining, enables a second address to be presented to a PLB slave while the
slave is transferring data associated with the first address. Address pipelining can occur if
a data-access request is produced before all data from a previous request are transferred by
the slave. This capability maximizes PLB-transfer throughput by reducing dead cycles
between multiple requests. The DCU can pipeline up to two read requests and one write
request. (Multiple write requests cannot be pipelined.) A pipelined request is
communicated over the PLB two or more cycles after the prior request is acknowledged by
the PLB slave.
Unaligned Accesses
If necessary, the processor automatically decomposes accesses to unaligned operands into
two data-access requests that are presented separately to the PLB. This occurs if an
operand crosses a word boundary (for a word transfer) or a cache line boundary (for an
eight-word line transfer). For example, assume software reads the unaligned word at
address 0x1F. This word crosses a cache line boundary: the byte at address 0x1F is in one
cache line and the bytes at addresses 0x20:0x22 are in another cache line. If neither cache
line is in the data cache, two consecutive read requests are presented by the DCU to the
PLB slave. If one cache line is already in the data cache, only the missing portion is
requested by the DCU.
Because write requests are not address pipelined by the DCU, writes to unaligned data that
cross cache line boundaries can take significantly longer than aligned writes.
Guarded Storage
No bytes can be accessed speculatively from guarded storage. The PLB slave must return
only the requested data when guarded storage is read and update only the specified
memory locations when guarded storage is written. For single word transfers, only the
bytes indicated by the byte enables are transferred. For line transfers, all eight words in the
line are transferred.
Data-Side PLB Interface I/O Signal Table
Figure 2-15 shows the block symbol for the data-side PLB interface. The signals are
summarized in Table 2-12.