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190 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 4: PowerPC 405 APU Controller
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FCM User-Defined Instruction Decoding
User-defined instructions that are not recognized (i.e., decoded) by the APU Controller are
passed to the FCM for decoding in fabric logic. While this allows for more custom
instructions than the eight APU Controller decoded UDIs to be defined, additional
instructions come at an execution speed penalty. Decoding in the FCM is not as efficient as
in the APU Controller.
FCM decoded UDI instructions adhere to the same configuration rules as those decoded
by the APU Controller.
FCM Exceptions
The FCM can signal an exception (FCMAPUEXCEPTION) to the APU Controller while
executing blocking and non-blocking instructions. This causes (1) the APU Controller to
flush the FCM instruction (see “FCM Instruction Flushing”) and (2) the PowerPC to launch
the appropriate exception handler, provided the PowerPC MSR enables APU exceptions
(see “Enabling the APU Controller”).
To execute the exception routine, the PowerPC saves the return program counter in its
SSR0 register and the current value of MSR in the SSR1 register. The exception vector used
for FCM exceptions is 0x700. When an exception occurs during the execution of a floating
point instruction, bit 12 in the PowerPC ESR register is asserted. For exceptions during all
other types of instructions, bit 13 in the ESR is asserted instead.
To return from the exception the FCM must provide the processor some way to strike
down the FCMAPUEXCEPTION signal from the exception handler. This could be done
using, for example, a UDI or an external DCR bus access.
FCM Instruction Flushing
The APU Controller can request that an FCM instruction be flushed under certain
circumstances. If this happens, the FCM must be able to re-issue the same instruction
without corrupting its internal state. For each FCM instruction, the APU Controller signals
when the point-of-no-return has been reached (APUFCMWRITEBACKOK asserted), after
which no flush can be done. The conditions under which APUFCMWRITEBACKOK
asserts are as follows:
x The instruction is a non-blocking, multi-cycle operation and is currently in the last
cycle of execution (two FCM clock cycles after FCMAPUDONE asserted).
x The instruction is a Blocking or Autonomous multi-cycle in the first cycle of execution
(same cycle as APUFCMOPERANDVALID is asserted).
x Executing an FCM Load and the last word is in the PowerPC LoadWB stage.
x Executing an FCM Store with the APU Controller configuration register bit
StoreWBOK set, and return data has been committed to the PowerPC WriteBack
stage.
If the APU Controller configuration register bit StoreWBOK is not set, the
APUFCMWRITEBACKOK will not be asserted when a Store is executed.
Execution Hazards
The APU Controller ensures that there are no data or structural hazards with regard to the
PowerPC405 pipeline execution.