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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 233
UG018 (v2.0) August 20, 2004 1-800-255-7778
A
abort
data-side PLB
78, 97
instruction-side PLB 54, 67
address acknowledge
data-side PLB
80
instruction-side PLB 55
address bus
data-side PLB
74
DCR 105
instruction-side PLB 52
address pipelining
cacheable fetch
62, 63
cacheable reads 86
data 71
fetch requests 49
non-cacheable fetch 65
reads and writes 87, 92
addressing modes 23
B
big endian, definition of 23
bus-interface unit 59, 85
busy
data-side PLB
84
instruction-side PLB 58
bypass
data
70
instruction 48
byte enables 76
C
cacheability
data-side PLB 75
instruction-side PLB 53
CCR0
fetch without allocate
49, 53
load without allocate 70
load word as line 70
non-cacheable request size 48, 56
store without allocate 70
chip reset 43, 46
request 45
clock
PLB
37
PPC405 37
clock and power management
See CPM interface.
clock zone
35
condition register
See CR.
core clock zone
35, 37
core reset 43, 46
request 45
core-configuration register
See CCR0.
CPM interface
35
signals 36
CPU control
interface 41
CR 25
critical interrupt request 111
D
data-cache unit
See DCU.
data-side PLB interface
68
See also read request.
See also write request.
abort
78
address acknowledge 80
address bus 74
busy 84
byte enables 76
cacheability 75
error 84
guarded storage 76
priority 78
read acknowledge 82
read not write 74
read-data bus 82
request 73
signals 71
slave size 81
timing diagrams 85
transfer order 83
transfer size 74
U0 attribute 76
write acknowledge 83
write-data bus 79
write-through 75
DCR
and processor block timing model
223
DCR interface 25, 98
address bus 105
chain implementation 101
description of 30
read request 105
read-data bus 106
request acknowledge 106
write request 105
write-data bus 106
DCU
description of
28
fill buffer 70
debug halt mode 129
debug interface 128
bus hold acknowledge 129
debug halt 129
debug halt acknowledge 131
signals 128
unconditional debug event 130
wait-state enable 130
writeback complete 130
writeback full 130
writeback instruction address 130
debug modes 29
device-control register
See DCR interface.
DSPLB
See data-side PLB.
E
EIC interface 109
signals 110
error
data-side PLB
84
instruction-side PLB 59
exceptions
critical
27, 110
noncritical 27, 110
external interrupt controller
See EIC interface.
F
fetch request 47
address pipelining 49
Index