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70 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
i An eight-word line transfer moves the eight-word cache line aligned on the
address specified by C405PLBDCUABUS[0:26]. See “C405PLBDCUABUS[0:31]
(Output)”. This cache line contains the target data accessed by the DCU. The
cache line is transferred using four doubleword or eight word transfer operations,
depending on the PLB slave bus width (64-bit or 32-bit, respectively). The byte
enables are not used by the processor for this type of transfer and they must be
ignored by the PLB slave.
x The words read during a data-read transfer can be sent from the PLB slave to the DCU
in any order (target-word-first, sequential, other). This transfer order is specified by
PLBC405DCURDWDADDR[1:3]. See “PLBC405DCURDWDADDR[1:3] (Input)”. For
data-write transfers, data is transferred from the DCU to the PLB slave in ascending-
address order.
Interaction with the DCU Fill Buffer
As mentioned above, the PLB slave can transfer data to the DCU in any order (target-word-
first, sequential, other). When data is received by the DCU from the PLB slave, it is placed
in the DCU fill buffer. When the DCU receives the target (requested) data, it forwards it
immediately from the fill buffer to the load/store unit so that pipeline stalls due to load-
miss delays are minimized. This operation is referred to as a bypass. The remaining data is
received from the PLB slave and placed in the fill buffer. Subsequent data is read from the
fill buffer if the data is already present in the buffer. For the best possible software
performance, the PLB slave should be designed to return the target word first.
Non-cacheable data is usually transferred as a single word. Software can indicate that non-
cacheable reads be loaded using an eight-word line transfer by setting the load-word-as-line
bit in the core-configuration register (CCR0[LWL]) to 1. This enables non-cacheable reads
to take advantage of the PLB line-transfer protocol to minimize PLB-arbitration delays and
bus delays associated with multiple, single-word transfers. The transferred data is placed
in the DCU fill buffer, but not in the data cache. Subsequent data reads from the same non-
cacheable line are read from the fill buffer instead of requiring a separate arbitration and
transfer sequence across the PLB. Data in the fill buffer is read with the same performance
as a cache hit. The non-cacheable line remains in the fill buffer until the fill buffer is needed
by another line transfer.
Non-cacheable reads from guarded storage and all non-cacheable writes are transferred as
a single word, regardless of the value of CCR0[LWL].
Cacheable data is transferred as a single word or as an eight-word line, depending on
whether the transfer allocates a cache line. Transfers that allocate cache lines use eight-
word transfer sizes. Transfers that do not allocate cache lines use a single-word transfer
size. Line allocation of cacheable data is controlled by the core-configuration register. The
load without allocate bit CCR0[LWOA] controls line allocation for cacheable loads and the
store without allocate bit CCR0[SWOA] controls line allocation for cacheable stores. Clearing
the appropriate bit to 0 enables line allocation (this is the default) and setting the bit to 1
disables line allocation. The dcbt and dcbtst instructions always allocate a cache line and
ignore the CCR0 bits.
Data read during an eight-word line transfer (one that allocates a cache line) is placed in
the DCU fill buffer as it is received from the PLB slave. Cacheable writes that allocate a
cache line also cause an eight-word read transfer from the PLB slave. The cacheable write
replaces the appropriate bytes in the fill buffer after they are read from the PLB.
Subsequent data accesses to and from the same cacheable line access the fill buffer during
the time the remaining bytes are transferred from the PLB slave. When the fill buffer is full,
its contents are transferred to the data cache.