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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 213
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
Appendix B
Signal Summary
Interface Signals
Table B-1 lists the PowerPC 405 interface signals in alphabetical order. A cross reference is
provided to each signal description. The signal naming conventions used are described in
“Signal Naming Conventions” in Chapter 2.
Table B-1: PowerPC 405 Interface Signals in Alphabetical Order
Signal
FPGA
Type
a
I/O
Type
Interface
If Unused
Ties To:
b
Function
APUFCMDECODED V-4 O FCM No
Connect
Indicates APU Controller decoded
FCM instruction.
APUFCMDECUDI[0:2] V-4 O FCM No
Connect
Indicates which UDI is decoded
(binary encoded).
APUFCMDECUDIVALID V-4 O FCM No
Connect
Valid signals for APUFCMDECUDI.
APUFCMENDIAN V-4 O FCM No
Connect
Indicates load/store instruction has
true little-endian storage attribute.
APUFCMFLUSH V-4 O FCM No
Connect
Flush APU instruction in the FCM.
APUFCMINSTRUCTION[0:31] V-4 O FCM No
Connect
Instruction being presented to the
FCM.
APUFCMINSTRVALID V-4 O FCM No
Connect
Valid APU instruction decoded by
APU Controller, or instruction passed
to FCM for decoding.
APUFCMLOADBYTEEN[0:3])V-4OFCMNo
Connect
Specifies the valid bytes for the word
on APUFCMLOADDATA.
APUFCMLOADDATA[0:31] V-4 O FCM No
Connect
Data word loaded from storage to the
APU register file.
APUFCMLOADDVALID V-4 O FCM No
Connect
Data valid signal for
APUFCMLOADDATA.
APUFCMOPERANDVALID V-4 O FCM No
Connect
Instruction operand valid.
APUFCMRADATA[0:31] V-4 O FCM No
Connect
Instruction operand from GPR(RA).
APUFCMRBDATA[0:31] V-4 O FCM No
Connect
Instruction operand from GPR(RB).
APUFCMWRITEBACKOK V-4 O FCM No
Connect
Safe for FCM to commit internal state
change.