Filter
Top Products
204 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 4: PowerPC 405 APU Controller
R
Note: Load data can arrive at the same time as the instruction or at a later clock cycle than shown
in Figure 4-8. Also, load data might not be sent back-to-back. Users should look at the valid signal.
FCM Store Instruction
Figure 4-8: APU Controller Decoded a Double Word Load Instruction with LoadWait Example
UG018_04_07_042304
CPMFCMCLK
APUFCMINSTRUCTION
APUFCMINSTRVALID
APUFCMDECODED
APUFCMLOADDATA word0 word1
APUFCMLOADDVALID
FCMAPUDONE
FCMAPULOADWAIT
FCMAPUSLEEPNOTREADY
Figure 4-9: APU Controller Decoded Store Instruction
UG018_04_08_032504
CPMFCMCLK
APUFCMINSTRUCTION
APUFCMINSTRVALID
APUFCMDECODED
FCMAPURESULT
FCMAPUDONE
FCMAPUSLEEPNOTREADY