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130 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
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In systems that deactivate the clocks to manage power, the debug halt signal should be
used to restart the clocks (if stopped) to enable an external debugger to operate the
processor. After the debugger finishes its operation and deasserts the debug halt signal, the
clocks can be stopped to return the processor to sleep mode.
This is a positive active signal. However, the debug halt signal produced by the RISCWatch
debugger is negative active. FPGA logic that attaches to a RISCWatch debugger must
invert the signal before sending it to the PowerPC 405.
DBGC405UNCONDDEBUGEVENT (Input)
When asserted, this signal causes an unconditional debug event and sets the UDE bit in the
debug-status register (DBSR) to 1. When this signal is deasserted, the processor operates
normally. Software can initialize the PowerPC 405 debug resources to perform any of the
following operations when an unconditional debug event occurs:
x Cause a debug interrupt in internal debug mode.
x Stop the processor in external debug mode.
x Cause a trigger event on the processor block trace interface.
C405DBGWBFULL (Output)
When asserted, this signal indicates that the PowerPC 405 writeback-pipeline stage is full.
It also indicates that writeback instruction-address bus (C405DBGWBIAR[0:29]) contains a
valid instruction address. When deasserted, the writeback stage is not full and the contents
of the writeback instruction-address bus are not valid.
C405DBGWBIAR[0:29] (Output)
When the writeback-full signal (C405DBGWBFULL) is asserted, this bus contains the
address of the instruction in the PowerPC 405 writeback-pipeline stage. If the writeback-
full signal is not asserted, the contents of this bus are invalid.
C405DBGWBCOMPLETE (Output)
When asserted, this signal indicates that the instruction in the PowerPC 405 writeback-
pipeline stage is completing. The address of the completing instruction is contained on the
writeback instruction-address bus (C405DBGWBIAR[0:29]). If the writeback-complete
signal is not asserted, the instruction on the writeback instruction-address bus is not
completing. The writeback-complete signal is valid only when the writeback-full signal
(C405DBGWBFULL) is asserted. The signal is not valid if the writeback-full signal is
deasserted.
C405DBGMSRWE (Output)
This signal indicates the state of the MSR[WE] (wait-state enable) bit. When asserted, wait
state is enabled (MSR[WE]=1). When deasserted, wait state is disabled (MSR[WE]=0).
When in the wait state, the processor stops fetching and executing instructions, and no
longer performs memory accesses. The processor continues to respond to interrupts, and
can be restarted through the use of external interrupts or timer interrupts. Wait state can
also be exited when an external debug tool clears WE or when a reset occurs.