Filter
Top Products
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 89
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
The second word read (rw2) is requested by the DCU in cycle 7 and the BIU responds in the
same cycle. A single word is sent from the BIU to the DCU in cycle 8. The DCU uses the
byte enables to select the appropriate bytes from the read-data bus.
The third word read (rw3) is requested by the DCU in cycle 12 and the BIU responds in the
same cycle. A single word is sent from the BIU to the DCU in cycle 13. The DCU uses the
byte enables to select the appropriate bytes from the read-data bus.
DSPLB Three Consecutive Line Writes
The timing diagram in Figure 2-20 shows three consecutive eight-word line writes. It
provides an example of the fastest speed at which the DCU can request and send data over
the PLB. All writes are cacheable. Consecutive writes cannot be address pipelined between
the DCU and BIU.
The first line write (wl1) is requested by the DCU in cycle 3 in response to a cache flush
(represented by the flush1 transaction in cycles 1 through 2). The BIU responds in the same
cycle the request is made by the DCU. Data is sent from the DCU to the BIU in cycles 3
through 6.
The second line write (wl2) cannot be started until the first request is complete. This
request is made by the DCU in cycle 8 in response to the cache flush in cycles 3 through 4
(flush2). The BIU responds in the same cycle the request is made by the DCU. Data is sent
from the DCU to the BIU in cycles 8 through 11.
The DCU can queue two outstanding data-cache flush requests. In this example, a third
flush request cannot be queued until the first is complete. The third flush request (flush3)
is queued in cycles 8 and 9.
Figure 2-19: DSPLB Three Consecutive Word Reads
Cy cle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PLBCLK and CPMC405CLK
UG018_23_101701
PPC405 Outputs:
C405PLBDCUREQUEST
C405PLBDCURNW
C405PLBDCUABUS[0:31]
adr1 adr2 adr3
d1 d2 d3
val valval
C405PLBDCUBE[0:7]
C405PLBDCUWRDBUS[0:63]
C405PLBDCUSIZE2
DCU
rw2 rw3rw1
rw2 rw3rw1
rw2 rw3rw1
PLB/BIU Outputs:
PLBC405DCUADDRACK
PLBC405DCURDDBUS[0:63]
PLBC405DCURDWDADDR[1:3]
PLBC405DCURDDACK
PLBC405DCUWRDACK
PLBC405DCUBUSY