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160 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 3: PowerPC 405 OCM Controller
R
ISCNTL Registers
Table 3-11 and Table 3-12 describe the ISCNTL registers in Virtex-II Pro and Virtex-4
devices. For additional information, refer to Figure 3-13, page 164 (Virtex-II Pro) and
Figure 3-14, page 165 (Virtex-4).
Table 3-10: DSCNTL Register for Virtex-4
Bit 0 DSOCM Enable If set to 1, address decoding based on the value of DSARC will be
enabled. If set to 0, the content in DSARC will be ignored.
Bit 1 DISABLEOPERANDFWD If set to 1, load data from the DSOCM goes directly into a latch in
the processor block. This causes an additional cycle (a total of two
cycles) of latency between a load instructions which is followed by
an instruction that requires the load data as an operand.
If set to 0, load data from the DSOCM/ must pass through steering
logic before arriving at a latch. This causes a single cycle of latency
between a load instruction which is followed by an instruction that
requires the load data as an operand.
Bit 2 DSOCMBUSY This status bit can be used as a flag indicator to the FPGA fabric.
This is an optional signal.
Bit 3 Enable Auto Clock Ratio
Detection.
If set to 1, automatic clock ratio detection circuits will be enabled
and users do not need to setup the CPU Clock / DSOCM Clock ratio
in DSCNTL[4:7]. Additionally, when DSOCMMCM is read back, the
value of the auto-detected clock ratio is reflected in terms of the wait
state value. If set to 0, automatic clock ration detection will be
disabled and users need to setup CPU Clock/DSOCM Clock ratio
in DSCNTL[4:7]. This is an enhanced feature in Virtex-4 devices and
we recommend setting this bit to 1.
Bit 4:7 DSOCMMCM CPU Clock and OCM Clock ratio. For Virtex-4 devices, if Auto
Clock Ratio Detection is enabled users need not setup the ratio in
this field. Users can also read back this field to determine the clock
ratio detected by the circuits.
If Auto Clock Ratio Detection is disabled, users need to setup the
ratio in this field. Reading back from this field will return the
content set by users previously.
Table 3-11: ISCNTL Register for Virtex-II Pro
Bit 0 ISOCM Enable If set to 1, address decoding based on the value of ISARC will be
enabled. If set to 0, the content in ISARC will be ignored.
Bit 1:4 Reserved. This bit must be configured to 0.
Bit 5:7 ISOCMMCM CPU Clock and ISOCM Clock ratio. For Virtex-II Pro users, users
must setup the ratio in this field with valid clock ratios used in the
application system. Then the processor gasket will issue
appropriate transactions based on this ratio.