Filter
Top Products
234 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
R
cacheable 49
non-cacheable request size 48
prefetching 49
without allocate 49
FIT
description of
29
timer exception 39
update frequency 38
fixed-interval timer
See FIT.
G
general-purpose register
See GPR.
global clock gating
35
global local clock enables 35
global set reset 137
global write enable
effect on core clock zone
136
effect on JTAG clock zone 136
effect on timer clock zone 137
GPR 24, 26
guarded storage
data
71
data-side PLB 76
instruction 50
I
ICU
description of
28
fill buffer 48
line buffer 28
instruction-cache unit
See ICU.
instruction-side PLB interface
47
See also fetch request.
abort 54
address acknowledge 55
address bus 52
busy 58
cacheability 53
error 59
fetch request 47, 52
priority 54
read acknowledge 56
read-data bus 56
signals 50
slave size 55
timing diagrams 59
transfer order 57
transfer size 53
U0 attribute 54
interfaces
CPM
35
CPU control 41
data-side PLB 68
DCR 98
debug 128
EIC 109
instruction-side PLB 47
trace 131
ISPLB
See instruction-side PLB.
J
JTAG clock zone 35, 37
JTAG interface
signals
111
test reset 47
L
little endian, definition of 23
M
MAC 27
early out 42
machine check 43, 59, 84
machine-state register
See MSR.
memory-management unit
See MMU.
MMU
27
enable and disable 42, 135
most recent reset 43
MSR 25
critical-interrupt enable 38, 110
external-interrupt enable 38, 110
wait-state enable 39, 130
multiply accumulate
See MAC.
multiply, early out
42
N
noncritical interrupt request 111
O
OCM
and processor block timing model
223
OEA
See PowerPC.
operand forwarding, disabling
42
P
performance summary 31
PIT
description of
29
timer exception 39
update frequency 38
PLB
description of
30
priority, data-side 78
priority, instruction-side 54
PLB clock 37
PLB slave
aborting requests
54, 78
attaching to 32-bit slave 56, 76
busy 58, 84
detecting errors 59, 84
power-on reset 43
PowerPC
architecture
17
embedded-environment architecture
17
OEA 18, 19
UISA 18
VEA 18
PowerPC 405 processor block
timing model
223
PPC405 25 to 30
caches 28
central-processing unit 26
clock 37
debug resources 29
exception-handling logic 27
external interfaces 29
memory-management unit 27
performance 30
software features 21
timers 29
prefetch 49
privileged mode, definition of 22
processor block, definition of 17
processor local bus
See PLB.